Clocked latching circuits are widely used in computer sequential logic circuits. For properly timed operation, such circuits require timing or clocking signal inputs. The edge triggered polarity hold latch is a commonly used circuit type which detects the polarity of the input data signal at the moment of occurrence of the edge of the clock input signal. The circuit produces an output signal which is equal to the input data signal each time that the leading edge occurs of the input clock signal. The output signal remains fixed (latched) at that value until the occurrence of the next clock signal when the output signal becomes equal to the then existing data signal input.
All known prior art circuits of such type require the use of two non-overlapping clock signals for proper operation. Either the two clock signals are centrally generated and routed to the individual latches or the second clock signal is locally generated within each latch (as by means of a delay element) from a centrally generated first clock signal which is routed to the individual latches. Each of these two techniques entails speed disadvantages especially in high performance computers. A plurality of clock signals that can not be overlapped wastes valuable time in high performance machines.
U.S. Pat. No. 3,413,557, Gated Strobing Latch for Synchronizing Data in an Asynchronous System, G. R. Muhlenbruch et al., Nov. 26, 1968 and assigned to the assignee of the present invention, discloses a dual clock phase, edge triggered, polarity hold latch which is an example of the prior art described above wherein two clock signals are utilized, the second clock signal being locally generated, using a delay, from a centrally generated first clock signal.
Accordingly, it is desirable to devise a single clocked circuit of the type described.